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HCF4029B
PRESETTABLE UP/DOWN COUNTER BINARY OR BCD DECADE
s
s
s
s
s s s
s
s s
MEDIUM SPEED OPERATION : 8MHz (Typ.) at CL = 50pF and VDD - VSS = 10V MULTI-PACKAGE PARALLEL CLOCKING FOR SYNCHRONOUS HIGH SPEED OUTPUT RESPONSE OR RIPPLE CLOCKING FOR SLOW CLOCK INPUT RISE AND FALL TIMES "PRESET ENABLE" AND INDIVIDUAL "JAM" INPUTS PROVIDED BINARY OR DECADE UP/DOWN COUNTING BCD OUTPUTS IN DECADE MODE QUIESCENT CURRENT SPECIF. UP TO 20V STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"
DIP
SOP
ORDER CODES
PACKAGE DIP SOP TUBE HCF4029BEY HCF4029BM1 T&R HCF4029M013TR
DESCRIPTION HCF4029B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF4029B consists of a four stage binary or BCD-decade up/down counter with provisions for look ahead carry in both counting modes. The PIN CONNECTION
inputs consist of a single CLOCK, CARRY IN (CLOCK ENABLE), BINARY/DECADE, UP/ DOWN, PRESET ENABLE, and four individual JAM signals. Q1, Q2, Q3, Q4 and a CARRY OUT signal are provided as outputs. A high PRESET ENABLE signal allows information on the JAM INPUTS to preset the counter to any state asynchronously with the clock. A low on each JAM line, when the PRESET-ENABLE signal is high, resets the counter to its zero count. The counter advances one count at the positive transition of the clock when the CARRY-IN and PRESET ENABLE signals are low. Advancement is inhibited when the CARRY-IN or PRESET ENABLE signals are high. The CARRY-OUT
September 2002
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HCF4029B
signal is normally high and the counter reaches its maximum count in the UP mode or the minimum count in the DOWN mode provided the CARRY-IN signal is low. The CARRY-IN signal in the low state can thus be considered a CLOCK ENABLE. The CARRY-IN terminal must be connected to VSS when not in use. Binary counting is accomplished when the BINARY/DECODE input is high; the counter counts in the decade mode when the BINARY/DECADE input is low. The counter counts Up when to UP/DOWN INPUT is high, and Down when the UP/DOWN INPUT is low. Multiple packages can be connected in either a parallel clocking or a ripple clocking arrangement. Parallel clocking provides synchronous control and, hence, a faster response from all counting outputs. Ripple clocking allows for longer clock input rise and fall times.
IINPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No 15 5 SYMBOL NAME AND FUNCTION Clock Input Carry In Input Binary / Decade Select Up/Down Select Preset Enable Input Jam Input Signals Q Outputs Carry Out Outputs Negative Supply Voltage Positive Supply Voltage
CLOCK CARRY IN BINARY/ 9 DECADE 10 UP/DOWN PRESET 1 ENABLE 4, 12, 13, 3 JAM1 to JAM4 6, 11, 14, 2 Q1 to Q4 7 CARRY OUT VSS 8 16 VDD
FUNCTIONAL DIAGRAM
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TRUTH TABLE
CLOCK X X TE X L X H X
X: Don't Care
TRUTH TABLE
PE L H L H H J L X H X X Q L Q H Q Q Q H Q L Q NC Q NC UP/DOWN PRESET ENABLE CARRY IN CONTROL INPUT BIN/DEC LOGIC LEVEL H L H L H L H L ACTION Binary Count Decade Count Up Count Down Count Jam In No Jam No Counter Advance counter
LOGIC DIAGRAM
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TIMING CHART - Binary Mode
TIMING CHART - Decade Mode
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ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI II PD Top Tstg Supply Voltage DC Input Voltage DC Input Current Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Storage Temperature Parameter Value -0.5 to +22 -0.5 to VDD + 0.5 10 200 100 -55 to +125 -65 to +150 Unit V V mA mW mW C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol VDD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 20 0 to VDD -55 to 125 Unit V V C
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DC SPECIFICATIONS
Test Conditions Symbol Parameter VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 0.5/4.5 1/9 1.5/18.5 0.5/4.5 9/1 1.5/18.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 VO (V) IO VDD (A) (V) 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25C Min. Typ. 0.04 0.04 0.04 0.08 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 -3.2 -1 -2.6 -6.8 1 2.6 6.8 10-5 5 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 3.5 7 11 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 Max. 5 10 20 100 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 Value -40 to 85C Min. Max. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 -55 to 125C Min. Max. 150 300 600 3000 Unit
IL
Quiescent Current
A
VOH
High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current
VOL
VIH
VIL
<1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1
V
V
V
V
IOH
IOL
Output Sink Current Input Leakage Current Input Capacitance
0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18
mA
mA
II
any input any input
0.1
7.5
1
1
A
pF
CI
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
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DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25C, CL = 50pF, RL = 200K, tr = tf = 20 ns)
Test Condition Symbol Parameter VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 PRESET ENABLE tPLH tPHL Propagation Delay Time (Q Outputs) tPLH tPHL Propagation Delay Time (Carry Output) tW Minimum Preset Enable (Pulse Width) Minimum Preset Enable (Removal Time) 5 10 15 5 10 15 5 10 15 5 10 15 235 100 80 320 145 105 65 35 25 100 55 40 470 200 160 640 290 210 130 70 50 200 110 80 ns Min. Value (*) Typ. 250 120 90 280 130 95 100 50 40 90 45 30 Max. 500 240 180 560 260 190 200 100 80 180 90 60 15 15 15 60 20 12 340 140 100 ns Unit
tPLH tPHL Propagation Delay Time (Q Outputs) tPLH tPHL Propagation Delay Time (Carry Output) tTHL tTLH Transition Time (Q Outputs, Carry Output) tW Minimum Clock Pulse Width Clock Rise and Fall Time
ns
ns
ns
tr, tf (1)
ns
tsetup(2)
Minimum Setup Time (Carry Input) Minimum Setup Time (B/D or U/D) Maximum Clock Input Frequency
tsetup
fMAX
2 4 5.5
30 10 6 170 70 50 4 8 11
ns
ns
MHz
ns
ns
trem(2)
ns
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Test Condition Symbol Parameter VDD (V) PRESET ENABLE tPHL tPLH Propagation Delay Time (Carry Output) tsetup(3) Minimum Setup Time (Carry In) Minimum Hold Time (Carry In) 5 10 15 5 10 15 5 10 15 Min.
Value (*) Typ. 170 70 50 25 15 12 100 35 30 Max. 340 140 100 50 30 25 200 70 60
Unit
ns
ns
thold
ns
(*) Typical temperature coefficient for all VDD value is 0.3 %/C. (1) If more than one unit is cascated in the parallel clocked application tr should be made less than or equal to the sum of the fixed propagation delay at 15pF and the transition time of the carry output driving stage for the estimated capacitance load. (2) From Up/Down, Binary/Decade, Carry In or Preset Enable Control Inputs to Clock Edge. (3) From Carry In to Clock Edge.
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200K RT = ZOUT of pulse generator (typically 50)
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HCF4029B
WAVEFORM 1 : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 2 : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)
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Plastic DIP-16 (0.25) MECHANICAL DATA
mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch
P001C
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SO-16 MECHANICAL DATA
DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010
PO13H
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com
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